1. 毕业设计（论文）的内容和要求

ldo（low-dropout voltage regulator） 是一种线性稳压器，使用在其线性区域内运行的晶体管或场效应管（fet），从应用的输入电压中减去超额的电压，产生经过调节的输出电压。

本次设计的快速瞬态响应低压差线性稳压器主要包括五个组成部分，分别为：基准电路设计、比较器电路设计、功率管阵列，功率管阵列控制以及其他辅助电路设计。

本次设计利用cadence工具完成电路设计及仿真，具体的任务分解如下： 1.查阅相关资料，学习ldo的基本结构，确定ldo五个电路部分的设计方案及性能指标。

2. 参考文献

[1] D. Kim M. Seok "8.2 fully integrated low-drop-out regulator based on event-driven PI control" IEEE Int. Solid-State Circuits Conf. (ISSCC) Tech. Dig. Papers pp. 148-149 Jan. 2016. [2] Y. Li, X. Zhang, Z. Zhang and Y. Lian, "A 0.45-to-1.2-V Fully Digital Low-Dropout Voltage Regulator With Fast-Transient Controller for Near/Subthreshold Circuits," in IEEE Transactions on Power Electronics, vol. 31, no. 9, pp. 6341-6350, Sept. 2016. [3]W. Chen, S. Ping, T. Huang, Y. Lee, K. Chen and C. Wey, "A Switchable Digital#8211;Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique," in IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 740-750, March 2014. [4]M. Huang, Y. Lu, S. U and R. P. Martins, "An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 20-34, Jan. 2018. [5] M. A. Akram, W. Hong and I. Hwang, "Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency," in IEEE Transactions on Power Electronics, vol. 33, no. 9, pp. 8011-8019, Sept. 2018. [6]Yasuyuki Okuma et al., "0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS," IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, 2010, pp. 1-4. [7]L. G. Salem, J. Warchall and P. P. Mercier, "A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 35-49, Jan. 2018. [8] M. Huang, Y. Lu, S. Sin, S. U and R. P. Martins, "A Fully Integrated Digital LDO With Coarse#8211;Fine-Tuning and Burst-Mode Operation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 7, pp. 683-687, July 2016. [9]D. Kim and M. Seok, "A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture," in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 3071-3080, Nov. 2017. [10]Y. Lee et al., "8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 150-151. [11]M. Seok, ”Fully integrated low-drop-out regulator based on eventdriven PI control,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.Tech. Papers, Feb. 2016, pp. 148#8211;149 [12] J. Kim, H. Ham, and M. Seok, ”A 0.5 V-VIN 1.44 mA-class event-driven digital LDO with a fully integrated 100 pF output capacitor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 346#8211;347 [13] Y.-J. Lee et al., ”A 200-mA digital low drop-out regulator with coarsefine dual loop in mobile application processor,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 64#8211;76, Jan. 2017. [14] Y. H. Lee et al., ”A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm SoC for MIPS performance improvement,” IEEE J. Solid-State Circuits, vol. 48,no. 4, pp. 1018#8211;1030, Apr. 2013. [15]马亚东. 具有快速瞬态响应的低压差线性稳压器的分析与设计[D].电子科技大学,2017 [16]赵永刚. 无输出电容LDO的研究与设计[D].西安电子科技大学,2017. [17]曹龙兵. 无电容型低压差线性稳压器的研究[D].电子科技大学,2018. [18]董祖奇. 低压瞬态增强无片外电容LDO线性稳压器的研究与设计[D].西安电子科技大学,2017.

3. 毕业设计（论文）进程安排

2019-12-15～2018-12-31学习ldo的基本知识，了解基本电路结构，根据应用背景，确定技术指标。

2019-01-01～2019-01-15毕业设计开题 2019-01-16～2019-02-25查阅论文资料，寻找不同的ldo设计方案，并分析不同设计方案的优缺点。

2019-02-25～2019-03-01综合各类设计方案，确定自己的设计方案。