摘 要

乘法器是数字信号处理器中必不可少的运算单元, 是完成高性能实时数字信号处理和图像处理的关键所在。因此提高处理器的各项性能指标必须基于高性能乘法器的设计和实现，关于提高乘法器性能的研究具有重要意义。

部分积的产生、部分积的压缩和最终积的产生三个关键模块共同组成了乘法器运算。通过分析研究，产生模块确定采用修正的Booth编码使部分积数目减半，压缩模块采用华莱士树4：2压缩器将部分积压缩为2行，其压缩比是2：1。压缩后的2行部分积由快速超前进位加法器进行求和运算并获得最终的乘积。论文主要分析了高性能并行乘法器的设计原理。纠错字的消除使压缩模块减少一级压缩，最终的加法器采用改进的超前进位加法器进行设计，所设计的1616位乘法器与基于Booth编码和Wallace压缩树的乘法器相比在速度上有了较大的提高。使用Verilog HDL语言对1616位乘法器进行描述并在ModelSim平台上进行仿真验证。

关键词：乘法器，超前进位加法器，4-2压缩，booth编码，华莱士树

Abstract

Multiplier is an indispensible arithmetic unit in digital signal processors, which is the key to completing high-performance real-time digital signal processing and image processing. To improve the performance of processors, it is necessary to design a high-performance multiplier. Therefore, the study of high-performance multiplier has been a hot topic at home and abroad.

The multiplier operations include three key modules: partial product generation, partial product accumulation and final product generation. After in-depth analysis of algorithms and structure for these three modules, the Booth 2 algorithm is chosen in the partial product generation stage, Wallace compression tree based on a 4-2 compressor and its compression ratio is 2:1. Finally, a fast adder is used to add the remaining two rows of partial products and obtain the final product.

This paper mainly analyzes the design principles of high-performance parallel multiplier. The Booth encoding algorithm, Wallace compression tree and various typical adders are also discussed in this paper. Then, the sign bit expansion and error-correcting word generated by Booth encoding are demonstrated. A Wallace compression stage is saved by deleting the error-correcting word. A improved carry look-ahead adder is used in final stage. The design of a proposed bit high-speed multiplier is provided. All designs are described with VerilogHDL and verified by ModelSim platform. Synthesis results using Artisan SMIC 0.18-m standard-cell show that the proposed multiplier achieves significant improvement in delay compared with the conventional multiplier.

Key Words：Multiplier; Carry look-ahead adder; 4-2 Compressor; Booth Coding; Wallace tree

目录

摘要 I

Abstract II

第一章 绪论 1

1.1 乘法器概述 1

1.1.1 研究背景 1

1.1.2 国内外研究现状 1

1.2 毕业设计的具体任务 2

1.3 论文的总体安排 2

第二章 乘法器的基本结构 4

2.1 基础原理 4

2.2 乘法器的分类 4

2.3 本章小结 6

第三章 并行乘法器分模块研究 8

3.1 部分积产生模块 8

3.1.1 Booth编码算法 8

3.1.2 二阶Booth编码算法 9

3.1.3 修正的Booth电路 10

3.1.4 符号位 13

3.2 部分积压缩模块 14

3.2.1 3:2压缩器 15

3.2.2 4:2压缩器 16

3.2.3 华莱士树的结构 18

3.3 加法器的研究 19

3.3.1 加法器的原理 19

3.3.2 行波进位加法器 20

3.3.3 进位选择加法器 21

3.3.4 超前进位加法器 21

3.3.5 并行前缀加法器 23

3.4 本章小结 24

第四章 乘法器的总体设计及其验证 26

4.1 部分积产生模块的设计 26

4.2 部分积压缩模块的设计 29

4.3 32位加法器的模块 29

4.4 并行乘法器整体的设计 31

4.5 并行乘法器的仿真验证和性能分析 32

4.6 本章小结 33

第五章 总结与展望 34

5.1 工作总结 34

5.2 全文展望 34

参 考 文 献 35

致 谢 38

第一章 绪论